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the information contained in this document is being issued in advance of the production cycle for the device. the parameters for the device may change before final production or nec corporation, at its own discretion, may withdraw the device prior to its production. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 2002 mos integrated circuit pd161830 240-output tft-lcd source driver (compatible with 64-gray scales) preliminary product informartion document no. s16240ej2v0pm00 (2nd edition) date published july 2002 ns cp (k) printed in japan the mark shows major revised points. description the pd161830 is a source driver for tft-lcds supporting 64 gray-scale display and can operate with a supply voltage of 2.5 v for the logic block and 5.0 v for the driver block. data input as 6-bit x 3-dot digital data is output as 64 -corrected values using an internal d/a converter and 5 external power modules, thus achieving a 260,000-color (full-color) display. features ? cmos level input ? 240 outputs ? input of 6 bits (gray-scale data) by 3 dots ? capable of outputting 64 values by means of 5 external power modules and a d/a converter ? output dynamic range: v ss2 to v dd2 ? high-speed data transfer: f clk = 15 mhz max. (internal data transfer speed when operating at v dd1 = 2.5 v) ? level inversion -correction power supply is possible ? logic power supply voltage (v dd1 ): 2.2 to 3.6 v ? driver power supply voltage (v dd2 ): 4.5 to 5.5 v ordering information part number package pd161830p chip remark purchasing the above chip entail the exchange of documents such as a separate memorandum or product quality, so please contact one of our sales representatives.
preliminary product information s16240ej2v0pm 2 pd161830 1. block diagram sthl v dd1 (2.5 v) v ss1 v dd2 (5.0 v) v ss2 s 2 s 1 v 0 to v 4 d 00 to d 05 c 1 c 2 c 79 c 80 stb clk 80-bit bidirectional shift register data register latch level shifter d/a converter output buffer r,/l sthr d 10 to d 15 d 20 to d 25 s 3 s 240 ap ba cm inbuf mode control control bias control inv pol mode vcom buf vc sel vcom gam test o2 test o1 test in v dd1 remark /xxx indicates active low si gnal.
preliminary product information s16240ej1v0pm 3 pd161830 2. pin configuration (pad layout) chip size: 15.84 x 1.11 mm 2 bump size (input/vcom/test/dummy): 80 x 86 m 2 bump size (output): 29 x 103 m 2 alignment mark ( m) x: 7716.45 y: 347.04 x: ?7716.45 y: 347.04 y x 1 332 331 327 326 241 242 246 247 alignment mark shape (unit: m) 29.04 89.52 29.04 89.52
preliminary product information s16240ej2v0pm 4 pd161830 table 2?1. pad layout (1/2) no. name x [ m] y [ m] no. name x [ m] y [ m] no. name x [ m] y [ m] 1 s1 7170.000 396.480 61 s61 3570.000 396.480 121 s121 -30.000 396.480 2 s2 7110.000 396.480 62 s62 3510.000 396.480 122 s122 -90.000 396.480 3 s3 7050.000 396.480 63 s63 3450.000 396.480 123 s123 -150.000 396.480 4 s4 6990.000 396.480 64 s64 3390.000 396.480 124 s124 -210.000 396.480 5 s5 6930.000 396.480 65 s65 3330.000 396.480 125 s125 -270.000 396.480 6 s6 6870.000 396.480 66 s66 3270.000 396.480 126 s126 -330.000 396.480 7 s7 6810.000 396.480 67 s67 3210.000 396.480 127 s127 -390.000 396.480 8 s8 6750.000 396.480 68 s68 3150.000 396.480 128 s128 -450.000 396.480 9 s9 6690.000 396.480 69 s69 3090.000 396.480 129 s129 -510.000 396.480 10 s10 6630.000 396.480 70 s70 3030.000 396.480 130 s130 -570.000 396.480 11 s11 6570.000 396.480 71 s71 2970.000 396.480 131 s131 -630.000 396.480 12 s12 6510.000 396.480 72 s72 2910.000 396.480 132 s132 -690.000 396.480 13 s13 6450.000 396.480 73 s73 2850.000 396.480 133 s133 -750.000 396.480 14 s14 6390.000 396.480 74 s74 2790.000 396.480 134 s134 -810.000 396.480 15 s15 6330.000 396.480 75 s75 2730.000 396.480 135 s135 -870.000 396.480 16 s16 6270.000 396.480 76 s76 2670.000 396.480 136 s136 -930.000 396.480 17 s17 6210.000 396.480 77 s77 2610.000 396.480 137 s137 -990.000 396.480 18 s18 6150.000 396.480 78 s78 2550.000 396.480 138 s138 -1050.000 396.480 19 s19 6090.000 396.480 79 s79 2490.000 396.480 139 s139 -1110.000 396.480 20 s20 6030.000 396.480 80 s80 2430.000 396.480 140 s140 -1170.000 396.480 21 s21 5970.000 396.480 81 s81 2370.000 396.480 141 s141 -1230.000 396.480 22 s22 5910.000 396.480 82 s82 2310.000 396.480 142 s142 -1290.000 396.480 23 s23 5850.000 396.480 83 s83 2250.000 396.480 143 s143 -1350.000 396.480 24 s24 5790.000 396.480 84 s84 2190.000 396.480 144 s144 -1410.000 396.480 25 s25 5730.000 396.480 85 s85 2130.000 396.480 145 s145 -1470.000 396.480 26 s26 5670.000 396.480 86 s86 2070.000 396.480 146 s146 -1530.000 396.480 27 s27 5610.000 396.480 87 s87 2010.000 396.480 147 s147 -1590.000 396.480 28 s28 5550.000 396.480 88 s88 1950.000 396.480 148 s148 -1650.000 396.480 29 s29 5490.000 396.480 89 s89 1890.000 396.480 149 s149 -1710.000 396.480 30 s30 5430.000 396.480 90 s90 1830.000 396.480 150 s150 -1770.000 396.480 31 s31 5370.000 396.480 91 s91 1770.000 396.480 151 s151 -1830.000 396.480 32 s32 5310.000 396.480 92 s92 1710.000 396.480 152 s152 -1890.000 396.480 33 s33 5250.000 396.480 93 s93 1650.000 396.480 153 s153 -1950.000 396.480 34 s34 5190.000 396.480 94 s94 1590.000 396.480 154 s154 -2010.000 396.480 35 s35 5130.000 396.480 95 s95 1530.000 396.480 155 s155 -2070.000 396.480 36 s36 5070.000 396.480 96 s96 1470.000 396.480 156 s156 -2130.000 396.480 37 s37 5010.000 396.480 97 s97 1410.000 396.480 157 s157 -2190.000 396.480 38 s38 4950.000 396.480 98 s98 1350.000 396.480 158 s158 -2250.000 396.480 39 s39 4890.000 396.480 99 s99 1290.000 396.480 159 s159 -2310.000 396.480 40 s40 4830.000 396.480 100 s100 1230.000 396.480 160 s160 -2370.000 396.480 41 s41 4770.000 396.480 101 s101 1170.000 396.480 161 s161 -2430.000 396.480 42 s42 4710.000 396.480 102 s102 1110.000 396.480 162 s162 -2490.000 396.480 43 s43 4650.000 396.480 103 s103 1050.000 396.480 163 s163 -2550.000 396.480 44 s44 4590.000 396.480 104 s104 990.000 396.480 164 s164 -2610.000 396.480 45 s45 4530.000 396.480 105 s105 930.000 396.480 165 s165 -2670.000 396.480 46 s46 4470.000 396.480 106 s106 870.000 396.480 166 s166 -2730.000 396.480 47 s47 4410.000 396.480 107 s107 810.000 396.480 167 s167 -2790.000 396.480 48 s48 4350.000 396.480 108 s108 750.000 396.480 168 s168 -2850.000 396.480 49 s49 4290.000 396.480 109 s109 690.000 396.480 169 s169 -2910.000 396.480 50 s50 4230.000 396.480 110 s110 630.000 396.480 170 s170 -2970.000 396.480 51 s51 4170.000 396.480 111 s111 570.000 396.480 171 s171 -3030.000 396.480 52 s52 4110.000 396.480 112 s112 510.000 396.480 172 s172 -3090.000 396.480 53 s53 4050.000 396.480 113 s113 450.000 396.480 173 s173 -3150.000 396.480 54 s54 3990.000 396.480 114 s114 390.000 396.480 174 s174 -3210.000 396.480 55 s55 3930.000 396.480 115 s115 330.000 396.480 175 s175 -3270.000 396.480 56 s56 3870.000 396.480 116 s116 270.000 396.480 176 s176 -3330.000 396.480 57 s57 3810.000 396.480 117 s117 210.000 396.480 177 s177 -3390.000 396.480 58 s58 3750.000 396.480 118 s118 150.000 396.480 178 s178 -3450.000 396.480 59 s59 3690.000 396.480 119 s119 90.000 396.480 179 s179 -3510.000 396.480 60 s60 3630.000 396.480 120 s120 30.000 396.480 180 s180 -3570.000 396.480
preliminary product information s16240ej1v0pm 5 pd161830 table 2?1. pad layout (2/2) no. name x [ m] y [ m] no. name x [ m] y [ m] no. name x [ m] y [ m] 181 s181 -3630.000 396.480 241 dummy1 -7311.420 407.010 301 d11 2725.110 -407.010 182 s182 -3690.000 396.480 242 dummy2 -7772.010 164.880 302 d10 2975.130 -407.010 183 s183 -3750.000 396.480 243 dummy3 -7772.010 64.860 303 d05 3225.150 -407.010 184 s184 -3810.000 396.480 244 dummy4 -7772.010 -35.160 304 d04 3475.170 -407.010 185 s185 -3870.000 396.480 245 dummy5 -7772.010 -135.180 305 d03 3725.190 -407.010 186 s186 -3930.000 396.480 246 dummy6 -7772.010 -235.200 306 d02 3975.210 -407.010 187 s187 -3990.000 396.480 247 dummy7 -7654.530 -407.010 307 d01 4225.230 -407.010 188 s188 -4050.000 396.480 248 vcom -7479.510 -407.010 308 d00 4475.250 -407.010 189 s189 -4110.000 396.480 249 sthl -7229.490 -407.010 309 testo1 4725.270 -407.010 190 s190 -4170.000 396.480 250 dummy8 -7054.440 -407.010 310 testo2 4975.290 -407.010 191 s191 -4230.000 396.480 251 vdd2 -6793.050 -407.010 311 testin 5225.310 -407.010 192 s192 -4290.000 396.480 252 vdd2 -6693.090 -407.010 312 vdd1 5475.360 -407.010 193 s193 -4350.000 396.480 253 vdd2 -6593.130 -407.010 313 vdd1 5575.320 -407.010 194 s194 -4410.000 396.480 254 vdd1 -6331.710 -407.010 314 vdd1 5675.280 -407.010 195 s195 -4470.000 396.480 255 vdd1 -6231.750 -407.010 315 vss1 5853.630 -407.010 196 s196 -4530.000 396.480 256 vdd1 -6131.790 -407.010 316 vss1 5953.590 -407.010 197 s197 -4590.000 396.480 257 vss1 -5878.440 -407.010 317 vss1 6053.550 -407.010 198 s198 -4650.000 396.480 258 vss1 -5778.480 -407.010 318 vss2 6303.570 -407.010 199 s199 -4710.000 396.480 259 vss1 -5678.520 -407.010 319 vss2 6403.530 -407.010 200 s200 -4770.000 396.480 260 vss2 -5428.500 -407.010 320 vss2 6503.490 -407.010 201 s201 -4830.000 396.480 261 vss2 -5328.540 -407.010 321 vdd2 6843.180 -407.010 202 s202 -4890.000 396.480 262 vss2 -5228.580 -407.010 322 vdd2 6943.140 -407.010 203 s203 -4950.000 396.480 263 vcsel -4975.260 -407.010 323 vdd2 7043.100 -407.010 204 s204 -5010.000 396.480 264 r,/l -4725.240 -407.010 324 dummy11 7304.490 -407.010 205 s205 -5070.000 396.480 265 mode -4475.220 -407.010 325 sthr 7479.540 -407.010 206 s206 -5130.000 396.480 266 ba -4225.200 -407.010 326 dummy12 7654.560 -407.010 207 s207 -5190.000 396.480 267 gam -3975.180 -407.010 327 dummy13 7772.010 -235.200 208 s208 -5250.000 396.480 268 cm -3725.160 -407.010 328 dummy14 7772.010 -135.180 209 s209 -5310.000 396.480 269 pol -3475.140 -407.010 329 dummy15 7772.010 -35.160 210 s210 -5370.000 396.480 270 ap -3225.120 -407.010 330 dummy16 7772.010 64.860 211 s211 -5430.000 396.480 271 stb -2975.100 -407.010 331 dummy17 7772.010 164.880 212 s212 -5490.000 396.480 272 d25 -2725.080 -407.010 332 dummy18 7311.420 407.010 213 s213 -5550.000 396.480 273 d24 -2475.060 -407.010 214 s214 -5610.000 396.480 274 d23 -2225.040 -407.010 215 s215 -5670.000 396.480 275 d22 -1975.020 -407.010 216 s216 -5730.000 396.480 276 d21 -1725.000 -407.010 217 s217 -5790.000 396.480 277 d20 -1474.980 -407.010 218 s218 -5850.000 396.480 278 clk -1224.960 -407.010 219 s219 -5910.000 396.480 279 dummy9 -1049.910 -407.010 220 s220 -5970.000 396.480 280 v4 -874.860 -407.010 221 s221 -6030.000 396.480 281 v4 -774.900 -407.010 222 s222 -6090.000 396.480 282 v4 -674.940 -407.010 223 s223 -6150.000 396.480 283 v3 -424.920 -407.010 224 s224 -6210.000 396.480 284 v3 -324.960 -407.010 225 s225 -6270.000 396.480 285 v3 -225.000 -407.010 226 s226 -6330.000 396.480 286 v2 25.080 -407.010 227 s227 -6390.000 396.480 287 v2 125.040 -407.010 228 s228 -6450.000 396.480 288 v2 225.000 -407.010 229 s229 -6510.000 396.480 289 v1 475.020 -407.010 230 s230 -6570.000 396.480 290 v1 574.980 -407.010 231 s231 -6630.000 396.480 291 v1 674.940 -407.010 232 s232 -6690.000 396.480 292 v0 925.020 -407.010 233 s233 -6750.000 396.480 293 v0 1024.980 -407.010 234 s234 -6810.000 396.480 294 v0 1124.940 -407.010 235 s235 -6870.000 396.480 295 dummy10 1299.990 -407.010 236 s236 -6930.000 396.480 296 inv 1475.010 -407.010 237 s237 -6990.000 396.480 297 d15 1725.030 -407.010 238 s238 -7050.000 396.480 298 d14 1975.050 -407.010 239 s239 -7110.000 396.480 299 d13 2225.070 -407.010 240 s240 -7170.000 396.480 300 d12 2475.090 -407.010
preliminary product information s16240ej2v0pm 6 pd161830 3. pin functions (1/2) pin symbol pin name pad no. i/o description s 1 to s 240 driver output 1 to 240 output the d/a converted 64-gray-scale analog voltage is output. d 00 to d 05 308 to 303 d 10 to d 15 302 to 297 d 20 to d 25 display data input 277 to 272 input the display data is input with a width of 18 bits, viz., the gray scale data (6 bits) by 3 dots (1 pixels). d x0 : lsb, d x5 : msb r,/l shift direction control input 264 input these refer to the shift direction control input. the shift directions of the shift registers are as follows. r,/l = l (left shift): sthl (input), s 240 s 1 sthr (output) r,/l = h (right shift) : sthr (input), s 1 s 240 sthl (output) sthr right shift start pulse input/output 325 i/o sthl left shift start pulse input/output 249 i/o these refer to the start pulse i/o pins when driver ics are connected in cascade. fetching of display data starts when h is read at the rising edge of clk. r,/l = l (left shift): sthl input, sthr output r,/l = h (right shift): sthr input, sthl output clk shift clock input 278 input this pin is the shift clock input of the shift register. display data is captured into the data register at the rising edge. the start pulse output enters high level at the rising edge of the 80 th clock following the start pulse input, and becomes the start pulse of the next level driver. the 81th clock of the first driver becomes the start pulse input of the next driver stb latch input 271 input a timing signal that latches the contents of the data register. when an h level is read at the rising edge of clk, the contents of the data register are latched and transferred to the d/a converter, and analog voltage corresponding to the display data is output. also, because the internal operation via clk continues even after the stb latch, do not stop clk. the contents of the shift register are cleared at the rising edge of stb. following a 1-pulse input at startup, this ic will operate normally. note that the output switch is turned off at the rising edge of stb. for the stb input timing, refer to switching characteristics waveform. pol polarity inversion signal 269 input this pin inverts the output polarity. the polarity inversion signal data is captured at the rising edge of stb. the -resistor is switched in accordance with the positive/negative polarity. pol = l: negative polarity pol = h: positive polarity inv data inversion 296 input this pin inverts the input data. input data in synchronization with the shift clock. inv = l: normal input inv = h: data inversion input vcom com amplitude output 248 output this pin inverts the signal input from the pol pin and outputs it following conversion to the v dd2 potential at the rising edge of stb. when the vcom output is not used, vc sel must be fixed to l. vc sel com amplitude output fixing signal 263 input the vcom output is fixed to l. when the vcom output is not used, vc sel needs to be fixed to l. vc sel = l: vcom output fixed to l vc sel = h: vcom signal output in correspondence with pol signal cm 8-color display mode switching 268 input the operating mode is switched to 8-color mode. input data msb leads display data. in this mode, turn off the -resistor, amplifier, and bias circuit. however, when the - correction power supply is input externally, the -circuit current will flow continuously. cm = l: normal display mode cm = h: 8-color display mode
preliminary product information s16240ej1v0pm 7 pd161830 (2/2) pin symbol pin name pad no. i/o description ap output sw on/off 270 input mode = l this pin turns on/off the bias circuit and turns on the output sw and amplifier. when ap is h, the amplifier is set and the lcd is driving. the amplifier output and output sw are turned on at the rising edge of ap, starting the lcd drive. note that the output sw is turned off at the rising edge of stb and the output becomes hi-z (hi-z: high impedance). for details, refer to 4.1 drive timing by mode and ap signal. for the ap input timing, refer to switching characteristics waveform. mode = h a sauce driver output circuit is changed to an amplifier output by grand fixation. for details, refer to 4.1 drive timing by mode and ap signal. gam external -usage selection 267 input when the -correction power supply is input externally, switch gam to h. if two or more chips are used, be sure to input the -correction power supply externally. figure 4?4 shows an input example of the -correction power supply. gam = l: external -correction power supply not input (open) gam = h: external -correction power supply input mode driver output functional change 265 input the drive mode of the sauce driver output by ap pin is set up as follows. for details, please refer to 4.1 drive timing by mode and ap signal. mode = l: normal drive mode mode = h: grand output drive mode v 0 to v 4 -corrected power supplies 294 to 280 ? these pins input the -corrected power supplies from outside, the relationship below must be observed. also, be sure to stabilize the gray-scale-level power supply during gray-scale voltage output. v ss2 v 4 v 3 v 2 v 1 v 0 v dd2 ba bias current adjustment function 266 input this pin adjusts the bias current and through rate of amplifier inside ic. select either the high power mode or low power mode. in addition, as compared with the time of the low power mode, twice about as many bias current as this flows at the time of high power mode. ba = l: low power mode ba = h: high power mode test in test input pin 311 input set to h or leave open test o1 , test o2 test output pin 309, 310 output leave open. v dd1 logic power supply 254 to 256, 312 to 314 ? 2.2 to 3.6 v v dd2 driver power supply 251 to 253, 321 to 323 ? 4.5 to 5.5 v v ss1 logic ground 257 to 259, 315 to 317 ? ground v ss2 driver ground 260 to 262, 318 to 320 ? ground dummy1 to dummy18 dummy 241 to 247, 250, 279, 295, 324, 326 to 332 ? this pin is dummy. caution to avoid latchup failure, the sequence when turning on the power must be v dd1 logic input v dd2 gray-scale power supply (v 0 to v 4 ), and the reverse sequence when turning off the power. follow this sequence during shift periods as well.
preliminary product information s16240ej2v0pm 8 pd161830 4. display driving circuit the display driving circuit of pd161830 consists of -resistance and -selection switch (sw) which are shown below, a d/a converter, and an output stage. the function of each block is as follows. -resistance : it is string resistance for -curve. -selection switch (sw): change -curve at the time of a positive and a negative drive. d/a converter : choose an output voltage level from display data. output stage : it consists of amplifier for a drive and a switch for a voltage maintenance drive, and an inverter for 8 color displays. figure 4?1. output circuit image positive negative -selection sw dac sw v 0 v 10 amp out output for 8-color display
preliminary product information s16240ej1v0pm 9 pd161830 4.1 drive timing by mode and ap signal mode = l normal drive is selected when a mode pin is set as l. based on output stage construction, ap pin, stb pin, clk pin signal, and the relation of sn (sauce output) state are shown in the next figure. from 1 clock of a clk signal to 4 clock is used for the output stage after a stb standup, it carries out decoding to the latch output voltage level of display data, and transmits to an output circuit. the output circuit's having prevented from sn pin output compulsorily the output of the level which is not decided as a hi-z state from the standup of a stb signal to the standup of a clk signal 4 clock. when ap pin is l input after 4 clock rises, as for sn pin output, hi-z state is maintained, and an output circuit changes from the standup of ap pin input to an amp drive state. moreover, sn pin outputs that the notes 1 which pull up to the voltage (display data) level which requires the potential of a tft drain line, or are reduced note1 . when low power consumption is required, amp pin is switched from h to l, after a voltage level attain to requirement voltage level l, output circuit stage operation is changed into sw drive note2 , and it stabilizes a voltage level. since liquid crystal load is driven only by sw drive of -resistance direct file when referred to as ap = l before attainment of the level to demand, most time is needed for level attainment. since this timing (ap = h period) is dependent on the load conditions of liquid crystal, it is a real use tft panel and fully needs to be evaluated. notes 1. when it is always set as ap = h, sn pin starts an amp drive automatically after the standup of 4 clock. 2. at the time of sw drive, stop the bias current of an output stage amplifier circuit, and stop the consumption current of the output stage.
preliminary product information s16240ej2v0pm 10 pd161830 figure 4?2. output stage operation image v 0 v 10 amp out 4 clk amp off off amp on off amp off on hi-z state sw drive amp drive hi-z state amp drive sw drive selection sw + dac sw hi-z minimum period ap stb clk sn
preliminary product information s16240ej1v0pm 11 pd161830 examples of the input/output timing of each signal during white and black display in normal mode are shown below. figure 4?3. timing chart stb ap pol data data = 000000 data = 111111 vcom 260,000-color display mode (cm = l) undefined out hi-z hi-z hi-z hi-z black level black level white level white level 8-color display mode out white level white level black level black level lsb msb msb used in 8-color display mode
preliminary product information s16240ej2v0pm 12 pd161830 mode = h (gnd output driving) when a mode pin is set as h, the output change function by ap pin is changed as follows. ap pin sn pin (source output) drive l gnd output (v ss fixed) h normal amp operation as for sauce output, output is fixed to ground (v ss ) in falling of ap signal at the time of gnd output drive (mode = h). moreover, the return to an apm drive usually returns from the next stb = h period which latched ap = h by the rising edge of stb signal. the relationship of the clk signal at the time of a gnd output drive, a stb signal, ap signal, and sn state is shown as follows. sth clk stb ap mode "h" sampling sampling data sampling data sampling data pol data all = 0 s 1 to s 240 hi-z amp driving gnd amp driving the next stb = h output start which latched ap = h. latch ap = h hi-z
preliminary product information s16240ej1v0pm 13 pd161830 4.2 -correction power supply connection example the pd161830 enables customization of the -correction power supply on both the positive and negative polarity sides (refer to 6. relationship between input data and output voltage value ). consequently, a - correction power supply does not have to be input externally when a single source-driver chip is being used in the panel. multiple chips can also be used without having to input a -correction power supply externally because the error between the chips can be absorbed by shorting the -correction power supply pins, as shown in figure 4?4. figure 4?4. -correction power-supply connection example v dd2 v ss2 v 0 v 1 v 2 v 3 v 4 v ss2 v dd2 external power supply input open single chip v dd2 v ss2 v 0 v 1 v 2 v 3 v 4 v ss2 v dd2 v dd2 v ss2 v 0 v 1 v 2 v 3 v 4 v ss2 v dd2 multiple chips v dd2 v ss2 v 0 v 1 v 2 v 3 v 4 v ss2 v dd2 v n - v n short v dd2 v ss2 v 0 v 1 v 2 v 3 v 4 v ss2 v dd2 v dd2 v ss2 v 0 v 1 v 2 v 3 v 4 v ss2 v dd2 external power supply input external power supply input external power supply input external power supply input external power supply input
preliminary product information s16240ej2v0pm 14 pd161830 4.3 clk signal input input at least 4 clocks of the clk signal after the rising of the stb signal. stb clk sth internal latch signal1 internal latch signal2 internal latch signal3 /1 2 3 4 5 6 1 2 3 4 7 8 d 19 to d 21 note note note drive timing d 16 to d 18 d 13 to d 15 d 10 to d 12 d 7 to d 9 d 4 to d 6 d 1 to d 3 invalid note internal latch signal : it is the signal that do latch the display data put in data register in output latch circuit. 5. mode explanation normal mode/ 8-clor display mode cm pol data driver output status driver output (in normally white) msb = h white level display h msb = l black level display msb = h white level display h l msb = l 8-color mode black level display all bit = h white level display h all bit = l black level display all bit = h white level display l l all bit = l 260,000-color mode black level display
preliminary product information s16240ej1v0pm 15 pd161830 6. relationship between input data and output voltage value the relationship between input data and output voltage are shown in table 6 ? 2. any 3 major points v 1 to v 3 from the lcd panel -characteristics curve can be used as the external power supplies. the relationship v 0 to v 4 external power supplies and -correction resistance is shown in table 6 ? 1, figure 6 ? 1. table 6?1. relationship between external power supply pins and -correction resistance pin name voltage (v) resistance ( ? ) v 0 5.0 0 v 1 3.5 7,500 v 2 2.5 12,500 v 3 1.5 17,500 v 4 0 25,000 figure 6?1. relationship between external power supply pins and -correction resistance v 0 v 1 v 2 v 3 v 4 v dd2 v ss2 7500 ? 5000 ? 5000 ? 7500 ? this external power supply pins (v 0 to v 4 ) can customize the -correction voltage by selecting the desired voltage from one of 250 divisions of the string resistor between v ss2 and v dd2 , which generated -correction voltage. note that the voltage can be selected individually for both positive and negative polarity.
preliminary product information s16240ej2v0pm 16 pd161830 table 6 ? ? ? ? 2. relationship of input data and output voltage in the pd161830 t.b.d. remark t.b.d. (to be determined.)
preliminary product information s16240ej1v0pm 17 pd161830 6.1 connection between -correction resistance, power supply, and gnd pin connection of - compensation resistance power supply (v 0 to v 4 ) and a power supply pin (v dd2 and v ss2 ) is indicated below to be - compensation resistance of pd161830. by setup of a gam pin, as for -compensation resistance, connection changes the highest minimum potential between v dd2 to v ss2 or among v 0 to v 4 . figure 6 ? ? ? ? 2. gam pin function positive polarity -selectionsw v 0 v 4 v 1 v 2 v 3 gam gam sw1 sw2 sw1 sw2 sw1 sw2 gam = l gam = h v dd2 v ss2 negative polarity
preliminary product information s16240ej2v0pm 18 pd161830 7. relationship between input data and output pin data format: 6 bits x rgbs (3 dots) input width: 18 bits (1-pixel data) r,/l = h (right shift) output s 1 s 2 s 3 s 4 ... s 239 s 240 data d 00 to d 05 d 10 to d 15 d 20 to d 25 d 00 to d 05 ... d 10 to d 15 d 20 to d 25 r,/l = l (left shift) output s 1 s 2 s 3 s 4 ... s 239 s 240 data d 00 to d 05 d 10 to d 15 d 20 to d 25 d 00 to d 05 ... d 10 to d 15 d 20 to d 25
preliminary product information s16240ej1v0pm 19 pd161830 8. electrical specifications absolute maximum ratings (t a = 25 c, v ss1 = v ss2 = 0 v) parameter symbol rating unit logic part supply voltage v dd1 ?0.3 to +4.5 v driver part supply voltage v dd2 ?0.3 to +6.0 v input voltage v i ?0.3 to v dd1,2 + 0.3 v output voltage v o ?0.3 to v dd1,2 + 0.3 v operating ambient temperature t a ?20 to +75 c storage temperature t stg ?55 to +125 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating range (t a = ?20 to +75 c, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit logic part supply voltage v dd1 2.2 3.6 v driver part supply voltage v dd2 4.5 5.0 5.5 v high-level input voltage v ih 0.7 v dd1 v dd1 v low-level input voltage v il 00.3 v dd1 v -corrected voltage v 0 to v 4 v ss2 v dd2 v clock frequency f clk 15 mhz
preliminary product information s16240ej2v0pm 20 pd161830 electrical characteristics (t a = ?20 to +75 c, v dd1 = 2.2 to 3.6 v, v dd2 = 5.0 v 0.5 v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit input leak current i il d 00 -d 05 , d 10 -d 15 , d 20 -d 25 , r,/l, stb, clk, sthr(l), inv, cm, ap, ba, pol, gam, vc sel 1.0 a input current i il2 test in 10 40 200 a high-level output voltage v oh sthr (sthl), i oh = ?1.0 ma v dd1 ? 0.5 v low-level output voltage v ol sthr (sthl), i ol = +1.0 ma 0.5 v v oh2 v dd2 = 5.0 v, i o = ?1.0 ma v dd2 ? 0.5 v vcom output voltage v ol2 v dd2 = 5.0 v, i o = +1.0 ma 0.5 v -correction power-supply static current consumption i v 0 = 5.0 v, v 4 = 0 v (when in -correction power mode) 100 200 400 a i voh1 v dd2 = 5.0 v, v out = v x ? 1.0 v note1 input data: 1fh ? 0.5 ? 0.15 ma driver output current (amp drive) i vol1 v dd2 = 5.0 v, v out = v x + 1.0 v note1 input data: 20h 0.15 0.50 ma i voh2 v dd2 = 5.0 v, v out = v x ? 1.0 v note1 input data: 1fh ? 50 ? 15 a driver output current (switch drive) i vol2 v dd2 = 5.0 v, v out = v x + 1.0 v note1 input data: 20h 15 40 a v voh3 v dd2 = 5.0 v, i o = ?50 av dd2 ? 0.5 v driver output current (8-color display mode) v vol3 v dd2 = 5.0 v, i o = +50 a0.5v output voltage deviation ? v o v dd1 = 2.5 v, v dd2 = 5.0 v, v out = 2.5 v note1 10 20 mv output voltage range v o input data: 00h to 3fh v ss2 + 0.05 v dd2 ? 0.05 v logic part dynamic current consumption i dd1 with no load note2 0.4 0.8 ma driver part dynamic current consumption i dd2 v dd = 5.0 v, with no load note2 0.9 1.5 ma notes 1. v x refers to the output voltage of analog output pins s 1 to s 240 . v out refers to the voltage applied to analog output pins s 1 to s 240 . 2. f clk = 15 mhz, stb cycle = 60 s, ap pulse width = 15 s, ba=l (low power mode)
preliminary product information s16240ej1v0pm 21 pd161830 switching characteristics (t a = ?20 to +75 c, v dd1 = 2.2 to 3.6 v, v dd2 = 5.0 v 0.5 v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit t plh1 25 ns start pulse delay time t phl1 c l = 15 pf 25 ns t plh2h 12 s driver output delay time (high power mode) t phl2h c l = 30 pf ap v out ? 100 mv or v out + 100 mv 12 s t plh2l 15 s driver output delay time (low power mode) t phl2l c l = 30 pf ap v out ? 100 mv or v out + 100 mv 15 s c i1 v 0 to v 4 , t a = 25c 5 15 pf input capacitance c i2 excluded v 0 to v 4 , t a = 25c 10 15 pf timing requirements (t a = ?20 to +75 c, v dd1 = 2.2 to 3.6 v, v ss1 = 0 v, t r = t f = 10 ns) parameter symbol condition min. typ. max. unit clock pulse width pw clk 65 ns clock pulse high period pw clk(h) 20 ns clock pulse low period pw clk(l) 20 ns data setup time t setup1 20 ns data hold time t hold1 20 ns start pulse setup time t setup2 20 ns start pulse hold time t hold2 20 ns start pulse low period t spl 3clk last data timing t ldt 2clk clk-stb time t clk-stb clk stb 20 ns stb pulse width pw stb 40 ns start pulse rising time t stb-sth stb sth 3clk inv set-up time t setup3 20 ns inv hold time t hold3 20 ns stb set-up time t setup4 20 ns stb hold time t hold4 20 ns pol-stb time t pol-stb 0ns stb-pol time t stb-pol 40 ns cm-stb time t cm-stb 0ns stb-cm time t stb-cm 40 ns stb-ap time t stb-ap stb ap 20 s ap pulse width (high power mode) pw aph 12 s ap pulse width (low power mode) pw apl stb cycle 40 s, c l = 30 pf 15 s ap set-up time t setup5 stb , mode = h 0 ns ap hold time t hold5 stb , mode = h 40 ns
preliminary product information s16240ej2v0pm 22 pd161830 switching characteristic waveform (r,/l= h) unless otherwise specified, the input level is defined to be v ih = 0.7 v dd1 , v il = 0.3 v dd1 . pw clk(l) clk pol v out stb data sthr sthl pw clk(h) t r t setup2 invalid d 1 to d 3 t hold2 123 80 81 t f pw clk t plh1 t stb-ap t setup1 90% 10% t hold1 t stb-sth pw stb t hold3 t hold4 t setup4 t spl pw ab d 4 to d 6 t pol-stb t stb-pol (1st dr.) (1st dr.) inv cm ap t phl1 t setup3 t cm-stb t stb-cm t clk-stb t plh2 t phl2 hi-z hi-z t ldt last data invalid
preliminary product information s16240ej1v0pm 23 pd161830 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd161830 reference documents nec semiconductor device reliability/quality control system (c10983e) quality grades on nec semiconductor devices (c11531e) ? the information contained in this document is being issued in advance of the production cycle for the device. the parameters for the device may change before final production or nec corporation, at its own discretion, may withdraw the device prior to its production. ? no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. ? nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, c opyrights or other intellectual property rights of nec corporation or others. ? descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. ? while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. ? nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m5 98. 8

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